1. Field of the Invention
The present invention generally relates to the fabrication of field effect transistors (FETs) having lightly-doped drain (LDD) regions; more particularly, to the formation and removal of spacers used in the fabrication of LDD regions.
2. Description of the Related Art
Lightly-doped drain (LDD) regions have commonly been used to reduce the length of the channel region in an FET. Reducing the length of the channel region makes it possible to reduce the size of the FET. The reduction in the length of the channel region is made possible by providing LDD regions which separate the source and drain regions from the channel region, thereby reducing the electric field at the source and drain pinch-off regions, and thus increasing the channel breakdown voltage and reducing electron impact ionization (hot electron effects).
An FET having LDD regions is typically fabricated in an active region of a substrate. The active region has a P.sup.- -type background doping and is bounded by field oxide (FOX) regions which electrically isolate the FET from other devices formed in the same substrate. (Either N-type or P-type dopants may be utilized, and the following discussion refers only to N-type dopants for convenience only.) Conventional processing techniques are utilized to implant regions located at both ends of a gate with a light dose of an N-type dopant using the gate as a mask. Two N.sup.- regions formed by the implant define a channel underlying the gate. A spacer material layer is formed over the entire structure and etched so that spacers remain at the ends of the gate. These spacers overlie portions of the N.sup.- regions adjacent to the gate structures. Thereafter, a second implant is performed with a heavier dose of an N-type dopant to form N.sup.+ source and drain regions in the N.sup.- regions. During the second implant the spacers mask the underlying N.sup.- regions. The N.sup.- regions which do not receive the second implant become the LDD regions. Thus, the width of the spacers defines the width of the LDD regions.
The conventional manner of forming spacers is to perform a blanket etch of a spacer material layer provided over the entire area of the substrate. Because there are non-uniformities in the thickness of the spacer material layer, and because of non-uniformities of the etching rate over the entire wafer area, there are areas of the wafer where over-etching occurs and other areas where there is an incomplete removal of the spacer material layer. Conventionally, the spacer material layer is an oxide, and it is critical that the oxide layer be completely removed from the top of the source/drain regions. However, when the strength of the etchant and the etching time are adjusted to assure complete removal of the oxide from the source/drain regions, the etchant often removes material from the field oxide regions. Typically, 1,000-2,000 .ANG. of the field oxide is removed. Removal of the field oxide, referred to as oxide loss, reduces the threshold voltage of the FET, and thus is not desirable.
Further, it is desirable to select an etching time based on the desired width of the spacers, rather than basing the etching time on complete removal of the spacer material layer. While the channel breakdown voltage of a LDD FET and its ability to resist hot electron effects can be increased by increasing the width of the LDD regions, the LDD regions can increase the resistance of the transistor channel and degrade the current drive capability of the FET. Consequently, it is important to control the fabrication process so that an optimum LDD width is achieved.
One proposed method of reducing oxide loss is to form the spacer material layer from a thin layer of a thermal oxide, e.g., SiO.sub.2, (for protecting the substrate) and a thicker layer of polysilicon overlying the thermal oxide. The polysilicon layer is then etched with an etchant which has a much higher etch rate for polysilicon than for the silicon oxide to form the spacers at the ends of the gate. Because the etchant selectively etches polysilicon, the oxide layer protects the underlying FOX regions from etching, thereby preventing oxide loss.
It is, however, very difficult to remove the polysilicon spacers after the N.sup.+ implant since the implant process oxidizes the surface of the polysilicon. Once an oxide layer forms at the surface of the polysilicon, an etchant which is chosen because it will selectively etch polysilicon at a much faster rate than it will etch oxides of silicon loses its selectivity and becomes ineffective for its desired purpose. The device must be exposed to the etchant for a period which is long enough for the etchant to penetrate the oxide skin on the polysilicon spacers, usually a period which allows the etchant to penetrate the oxide layer protecting the source, drain and FOX regions. After penetrating the protective oxide layer, the etchant will attack the substrate in the source and drain regions and the FOX regions causing oxide loss.